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pin configuration (top view) package type : 64p6n-a/64p6q-a description the 38C2 group is the 8-bit microcomputer based on the 740 family core technology. the 38C2 group has an lcd drive control circuit, a 10-channel a-d converter, and a serial i/o as additional functions. the various microcomputers in the 38C2 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. features basic machine-language instructions ....................................... 71 the minimum instruction execution time .......................... 0.25 s (at 8mhz oscillation frequency) memory size rom ................................................................ 16 k to 60 k bytes ram ................................................................. 640 to 2048 bytes programmable input/output ports ............................................. 51 (common to seg: 24) interrupts ................................................... 18 sources, 16 vectors timers ............................................................ 8-bit ? 4, 16-bit ? 2 a-d converter ................................................. 10-bit ? 8 channels serial i/o ........................ 8-bit ? 2 (uart or clock-synchronized) pwm .................. 10-bit ? 2, 16-bit ? 1 (common to igbt output) lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ........................................................................... 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ........................................................................ 24 two clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) watchdog timer ............................................................... 8-bit ? 1 led direct drive port .................................................................. 8 (average current: 15 ma, peak current: 30 ma, total current: 90 ma) power source voltage in through mode .......................................................... 4.0 to 5.5 v (at 8 mhz oscillation frequency) in frequency/2 mode ................................................... 1.8 to 5.5 v (at 4 mhz oscillation frequency, a-d operation excluded) in low-speed mode ..................................................... 1.8 to 5.5 v (at 32 khz oscillation frequency) power dissipation in through mode ................................................................. 26 mw (at 8 mhz oscillation frequency, v cc = 5 v) in low-speed mode ............................................................. 21 w (at 32 khz oscillation frequency, v cc = 3 v) operating temperature range ................................... C 20 to 85c fig. 1 m38C2xmx-xxxfp pin configuration 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p 0 6 / s e g 6 p 0 7 / s e g 7 p 1 0 / s e g 8 p 1 1 / s e g 9 p 1 2 / s e g 1 0 p 1 3 / s e g 1 1 p 1 4 / s e g 1 2 p 1 5 / s e g 1 3 p 1 6 / s e g 1 4 p 1 7 / s e g 1 5 p 6 0 / c n t r 1 p 3 7 / c n t r 0 / ( l e d 7 ) 61 3 2 3 1 30 29 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 67891 011121 31 4151 6 4 5444 34 24 140 3 93 83 7363 53 43 3 p2 4 /seg 20 p2 5 /seg 21 com 2 com 1 com 0 p2 7 /seg 23 /v l2 p2 6 /seg 22 /v l1 c o m 3 ( k w 7 ) / p 0 3 / s e g 3 p 0 4 / s e g 4 p 0 5 / s e g 5 p5 1 /int 1 ( k w 2 ) / p 5 6 / s c l k 1 ( k w 1 ) / p 5 5 / t x d 1 ( k w 0 ) / p 5 4 / r x d 1 p 5 3 / t 4 o u t / p w m 1 p 2 0 / s e g 1 6 p 2 1 / s e g 1 7 p 2 2 / s e g 1 8 p 2 3 / s e g 1 9 4 9 5 0 5 1 5 2 5 3 4 84 74 6 6 2 6 3 6 4 1234 5 2 0 19 1 8 1 7 5 5 5 6 5 7 5 8 59 60 m 3 8 c 2 x m x - x x x f p 5 4 p 3 6 / t 2 o u t / / ( l e d 6 ) x o u t p 5 2 / t 3 o u t / p w m 0 vre f v l3 p 4 3 / a n 3 p 4 2 / a n 2 p 4 4 / a n 4 p 4 7 / r t p 1 / a n 7 p 4 6 / r t p 0 / a n 6 p 4 5 / a n 5 v s s p 3 2 / t x d 2 / ( l e d 2 ) p3 1 /s clk2 /(led 1 ) p3 3 /r x d 2 /(led 3) p 5 0 / i n t 0 av s s ( k w 6 ) / p 0 2 / s e g 2 ( k w 5 ) / p 0 1 / s e g 1 ( k w 4 ) / p 0 0 / s e g 0 p 4 1 / o o u t 1 / a n 1 p 4 0 / o o u t 0 / a n 0 c n v s s p 6 2 / x c o u t p 6 1 / x c i n v c c x i n r e s e t ( k w 3 ) / p 5 7 / s r d y 1 p 3 0 / s r d y 2 / ( l e d 0 ) p 3 5 / t x o u t / ( l e d 5 ) p 3 4 / i n t 2 / ( l e d 4 ) preliminar y notice: this is not a final specification. some parametric limits are subject to change.
2 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. functional block diagram fig. 2 functional block diagram t i m e r t i m e r x ( 1 6 b i t s ) p w m ( 1 6 b i t s ) i g b t o u t p u t t i m e r y ( 1 6 b i t s ) t i m e r 1 ( 8 b i t s ) t i m e r 2 ( 8 b i t s ) t i m e r 3 ( 8 b i t s ) p w m 0 ( 1 0 b i t s ) t i m e r 4 ( 8 b i t s ) p w m 1 ( 1 0 b i t s ) p o r t p 0 ( 8 ) 8 p o r t p 1 ( 8 ) 8 p o r t p 2 ( 8 ) 8 i n t e r n a l p e r i p h e r a l f u n c t i o n a - d c o n v e r s i o n 1 0 - b i t ? 8 - c h a n n e l s e r i a l i / o s e r i a l i / o 1 ( u a r t o r c l o c k s y n c h r o n o u s ) s e r i a l i / o 2 ( u a r t o r c l o c k s y n c h r o n o u s ) l c d d r i v e c o n t r o l c i r c u i t 4 c o m ? 2 4 s e g s y s t e m c l o c k g e n e r a t i o n x i n C x o u t ( m a i n c l o c k ) x c i n C x c o u t ( s u b - c l o c k ) m e m o r y r o m r a m f o r l c d d i s p l a y ( 1 2 b y t e s ) r a m c p u c o r e w a t c h d o g t i m e r 8 8 p o r t p 4 ( 8 ) p o r t p 5 ( 8 ) p o r t p 6 ( 3 ) p o r t p 3 ( 8 ) 8 3
3 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. ? apply voltage of 1.8 v to 5.5 v to v cc , and 0 v to v ss . ? reference voltage input pin for a-d converter. ? gnd input pin for a-d converter. connect to v ss . ? reset input pin for active l. ? input and output pins for the main clock generating circuit. ? feedback resistor is built in between x in pin and x out pin. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to x in , and leave x out pin open. ? input 0 v l1 v l2 v l3 v cc voltage. ? input 0 C v l3 voltage to lcd. ? lcd common output pins. ? com 2 and com 3 are not used at 1/2 duty ratio. ? com 3 is not used at 1/3 duty ratio. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each port to be individually programmed as either input or output. ? pull-up control is enabled. v cc , v ss v ref av ss reset x in v l3 com 0 C com 3 p0 0 /seg 0 C p0 3 /seg 3 p0 4 /seg 4 C p0 7 /seg 7 p1 0 /seg 8 C p1 7 /seg 15 p2 0 /seg 16 C p2 5 /seg 21 p2 6 /seg 22 /v l1 p2 7 /seg 23 /v l2 p3 0 /s rdy2 p3 1 /s clk2 p3 2 /txd 2 p3 3 /rxd 2 p3 4 /int 2 p3 5 /t xout p3 6 /t 2out / p3 7 /cntr 0 p4 0 /o out0 /an 0 p4 1 /o out1 /an 1 p4 2 /an 2 C p4 5 /an 5 p4 6 /rtp 0 /an 6 p4 7 /rtp 1 /an 7 p5 0 /int 0 p5 1 /int 1 p5 2 /t 3out /pwm 0 p5 3 /t 4out /pwm 1 p5 4 /rxd 1 p5 5 /txd 1 p5 6 /s clk1 p5 7 /s rdy1 power source analog reference voltage analog power source reset input clock input lcd power source common output i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 function except a port function pin description table 1 pin description (1) function pin name ? lcd segment output pins ? serial i/o2 function pins ? external interrupt pin ? timer x, timer 2 output pins ? timer x function pin ? ad converter input pins ? external interrupt pins ? timer 3, timer 4 output pins ? pwm output pins ? serial i/o1 function pins ? key input interrupt input pins ? key input interrupt pins ? lcd power source input pins ? oscillation external output pins ? real time port function pins x out clock output
4 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. function except a port function pin description table 2 pin description (2) function pin name p6 0 /cntr 1 p6 1 /x cin p6 2 /x cout cnv ss i/o port p6 cnv ss ? 3-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? v pp power input pin in the flash mode. when mcu is operating, connect to v ss . ? timer y function pin ? i/o pins for sub-clock generating circuit. connect oscillators to them.
5 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. part numbering fig. 3 part numbering m38C2 9 m c C xxx hp product rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m f : mask rom version : flash memory version ram size 0 1 2 3 4 5 6 7 8 9 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes package type fp hp rom number omitted in flash memory version. characteristics C : standard d : extended operating temperature version : 64p6n-a package : 64p6q-a package 9 a b c d e f : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes
6 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. group expansion mitsubishi plans to expand the 38C2 group as follows. memory type support for mask rom, flash-memory versions memory size rom/flash memory size ...................................... 16 k to 60 k bytes ram size ............................................................. 640 to 2048 bytes memory expansion plan fig. 4 memory expansion plan currently supported products are listed below. as of may 2000 package 64p6n-a 64p6q-a 64p6n-a 64p6q-a 64p6n-a 64p6q-a 64p6n-a 64p6q-a product name rom size (bytes) rom size for user in ( ) 49152 (49022) 24576 (24446) 16384 (16254) 61440 (61310) ram size (bytes) 2048 640 640 2048 table 3 support products mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version flash memory version flash memory version remarks packages 64p6q-a ..................................... 0.5 mm-pitch plastic molded qfp 64p6n-a ..................................... 0.8 mm-pitch plastic molded qfp products under development or planning : the development schedule and specification may be revised without notice. rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 256 384 512 640 768 896 1024 192 ram size (bytes) 40k 48k 56k 60k under development under development under development 1536 2048 m38C24m6 m38C24m4 m38C29ff under development m38C29mc m38C29mc-xxxfp m38C29mc-xxxhp m38C24m6-xxxfp m38C24m6-xxxhp m38C24m4-xxxfp m38C24m4-xxxhp m38C29fffp m38C29ffhp
7 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. functional description central processing unit (cpu) the 38C2 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instruc- tions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the con- tents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and pop- ping them from the stack are shown in figure 6. store registers other than those described in figure 6 with program when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit regis- ters pc h and pc l . it is used to indicate the address of the next in- struction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
8 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) C 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) C 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) ( s ) ( s ) C 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
9 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic opera- tion and 3 flags which decide mcu operation. branch operations can be performed by testing the carry (c) flag , zero (z) flag, over- flow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ? bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ? bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . ? bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . ? bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ? bit 4: break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . ? bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed be- tween accumulator and memory. when the t flag is 1 , direct arith- metic operations and direct data transfers are enabled between memory locations. ? bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ? bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag C C i flag sei cli d flag sed cld b flag C C t flag set clt v flag C clv n flag C C
10 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the control bit for the internal system clock. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register not available processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : ram in the zero page is used as stack area 1 : ram in page 1 is used as stack area not used (returns 1 when read) (do not write 0 to this bit.) main clock (x in C x out ) d ivision ratio selection bits b5 b4 0 0 : x in /8 (frequency/8 mode) 0 1 : x in /4 (frequency/4 mode) 1 0 : x in /2 (frequency/2 mode) 1 1 : x in (through mode) system clock control bits b7 b6 0 0 : x in stop, x cin oscillating, system clock = x cin 0 1 : x in oscillating, x cin stop, system clock = x in 1 0 : x in oscillating, x cin oscillating, system clock = x cin 1 1 : x in oscillating, x cin oscillating, system clock = x in cpu mode register (cpum (cm) : address 003b 16 ) b7 b0
11 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. memory special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0 0 0 0 1 6 0 0 4 0 1 6 0 8 4 0 1 6 f f 0 0 1 6 f f d c 1 6 f f f e 1 6 f f f f 1 6 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 xxxx 16 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0 f 0 0 0 1 6 e 0 0 0 1 6 d 0 0 0 1 6 c 0 0 0 1 6 b 0 0 0 1 6 a 0 0 0 1 6 9 0 0 0 1 6 8 0 0 0 1 6 7 0 0 0 1 6 6 0 0 0 1 6 5 0 0 0 1 6 4 0 0 0 1 6 3 0 0 0 1 6 2 0 0 0 1 6 1 0 0 0 1 6 f 0 8 0 1 6 e 0 8 0 1 6 d 0 8 0 1 6 c 0 8 0 1 6 b 0 8 0 1 6 a 0 8 0 1 6 9 0 8 0 1 6 8 0 8 0 1 6 7 0 8 0 1 6 6 0 8 0 1 6 5 0 8 0 1 6 4 0 8 0 1 6 3 0 8 0 1 6 2 0 8 0 1 6 1 0 8 0 1 6 y y y y 1 6 z z z z 1 6 ram rom r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 rom area r o m s i z e ( b y t e s ) address yyyy 16 address zzzz 16 r e s e r v e d a r e a s f r a r e a n o t u s e d interrupt vector area r e s e r v e d r o m a r e a ( 1 2 8 b y t e s ) zero page s p e c i a l p a g e l c d d i s p l a y r a m a r e a r e s e r v e d r o m a r e a s f r a r e a 0 0 4 c 1 6 0 f e 0 1 6 1 0 00 1 6
12 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 9 memory map of special function register (sfr) 0ff9 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) a-d control register (adcon) a-d conversion register (low-order) (adl) a-d conversion register (high-order) (adh) interrupt control register 2 (icon2) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) timer 1 (t1) timer 3 (t3) pwm01 register (pwm01) timer 12 mode register (t12m) timer 2 (t2) timer 4 (t4) compare register (low-order) (compl) compare register (high-order) (comph) timer x (low-order) (txl) lcd power control register (vlcon) lcd mode register (lm) timer x (high-order) (txh) timer x (extension) (txex) 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0fe0 16 0fe1 16 0fe2 16 0fe6 16 0fe7 16 0fe9 16 0fe3 16 0fe4 16 0fe5 16 port p3 direction register (p3d) transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) transmit/receive buffer register 2 (tb2/rb2) serial i/o2 status register (sio2sts) uart1 control register (uart1con) serial i/o1 control register (sio1con) serial i/o2 control register (sio2con) baudrate generator 1 (brg1) baudrate generator 2 (brg2) uart2 control register (uart2con) 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 clock output control register (ckout) pull register (pull) timer 34 mode register (t34m) timer y (low-order) (tyl) timer y (high-order) (tyh) timer x mode register (txm) timer y mode register (tym) watchdog timer control register (wdtcon) 0ff8 16 0ffa 16 0ffb 16 0ffc 16 0ffd 16 0ffe 16 0fff 16 oscillation output control register (oscout) key input control register (kic) timer 1234 mode register (t1234m) timer x control register (txcon) timer 12 frequency division selection register (pre12) timer 34 frequency division selection register (pre34) timer xy frequency division selection register (prexy) segment output disable register 0 (seg0) segment output disable register 1 (seg1) segment output disable register 2 (seg2) timer y mode register 2 (tym2) flash memory control register (fmcr) reserved area 0fe8 16
13 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. i/o ports direction registers the i/o ports p0 C p6 have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit of the direction register, the correspond- ing pin becomes an input pin. as for ports p0 C p2, when 1 is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. as for ports p3 C p6, when 1 is written to the bit of the direction register, the corresponding pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are float- ing. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. pull-up control each individual bit of ports p0 C p2 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0ff8 16 to 0ffa 16 ). the pin is pulled up by setting 0 to the direction register and 1 to the segment output disable register. by setting the pull register (address 0ff1 16 ), ports p3 C p6 can con- trol pull-up with a program. however, the contents of pull register do not affect ports pro- grammed as the output ports. fig. 11 structure of pull register and segment output disable register fig. 10 structure of ports p0 to p2 s e g m e n t o u t p u t d i s a b l e r e g i s t e r d i r e c t i o n r e g i s t e r 0 1 0 1 i n p u t p o r t n o p u l l - u p s e g m e n t o u t p u t p o r t o u t p u t i n p u t p o r t p u l l - u p i n i t i a l s t a t e p3 0 C p3 3 pull-up p3 4 C p3 7 pull-up p4 0 C p4 3 pull-up p4 4 C p4 7 pull-up p5 0 C p5 3 pull-up p5 4 C p5 7 pull-up p6 0 C p6 2 pull-up not used (return 0 when read) pull register (pull : address 0ff1 16 ) b7 b0 p0 0 pull-up p0 1 pull-up p0 2 pull-up p0 3 pull-up p0 4 pull-up p0 5 pull-up p0 6 pull-up p0 7 pull-up segment output disable register 0 (seg0 : address 0ff8 16 ) b7 b0 note: the pull register and segment output disable register affect only ports programmed as the input ports. 0: no pull-up 1: pull-up p1 0 pull-up p1 1 pull-up p1 2 pull-up p1 3 pull-up p1 4 pull-up p1 5 pull-up p1 6 pull-up p1 7 pull-up b7 b0 segment output disable register 1 (seg1 : address 0ff9 16 ) p2 0 pull-up p2 1 pull-up p2 2 pull-up p2 3 pull-up p2 4 pull-up p2 5 pull-up p2 6 pull-up p2 7 pull-up b7 b0 segment output disable register 2 (seg2 : address 0ffa 16 ) 0: no pull-up 1: pull-up
14 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. name port p0 port p1 port p2 port p3 port p4 port p5 port p6 common input/output input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits output i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd common output non-port function lcd segment output serial i/o2 function i/o external interrupt input timer x output timer 2 output timer x function input a-d conversion input external interrupt input timer 3 output timer 4 output pwm output serial i/o1 function i/o timer y function input sub-clock oscillation circuit related sfrs segment output disable register 1 segment output disable register 2 segment output disable register 3 pull register serial i/o2 control register serial i/o2 status register uart2 control register pull register interrupt edge selection register pull register timer x mode register timer 12 mode register pull register timer x mode register pull register a-d control register pull register a-d control register timer y mode register pull register interrupt edge selection register pull register timer 12 mode register pull register serial i/o1 control register serial i/o1 status register uart1 control register pull register timer y mode register pull register cpu mode register lcd mode register ref. no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (7) (11) (10) (11) (7) (9) (12) (13) (14) (15) (7) (16) (17) (18) table 6 list of i/o port function notes 1: for details of how to use double/triple function ports as function i/o ports, refer to the applicable sections. 2: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. p0 0 /seg 0 C p0 3 /seg 3 p0 4 /seg 4 C p0 7 /seg 7 p1 0 /seg 8 C p1 7 /seg 15 p2 0 /seg 16 C p2 5 /seg 21 p2 6 /seg 22 /v l1 p2 7 /seg 23 /v l2 p3 0 /s rdy2 p3 1 /s clk2 p3 2 /txd 2 p3 3 /rxd 2 p3 4 /int 2 p3 5 /t xout p3 6 /t 2out / p3 7 /cntr 0 p4 0 /o out0 /an 0 p4 1 /o out1 /an 1 p4 2 /an 2 C p4 5 /an 5 p4 6 /rtp 0 /an 6 p4 7 /rtp 1 /an 7 p5 0 /int 0 p5 1 /int 1 p5 2 /t 3out /pwm 0 p5 3 /t 4out /pwm 1 p5 4 /rxd 1 p5 5 /txd 1 p5 6 /s clk1 p5 7 /s rdy1 p6 0 /cntr 1 p6 1 /x cin p6 2 /x cout com 0 C com 3 pin key input (key-on wakeup) interrupt input lcd power input oscillation external output real time port function output key input (key-on wakeup) interrupt input
15 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 12 port block diagram (1) ( 1 ) p o r t s p 0 0 C p 0 3 (3) port p3 0 data bus serial i/o output p o r t l a t c h p u l l - u p c o n t r o l serial i/o ready output data bus p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p u l l - u p c o n t r o l direction register data bus s e r i a l i / o i n p u t p o r t l a t c h data bus s e r i a l i / o c l o c k o u t p u t s e r i a l i / o c l o c k i n p u t serial i/o mode selection bi t serial i/o enable bi t port latch direction register p u l l - u p c o n t r o l s e g m e n t o u t p u t d i s a b l e b i t d a t a b u s p o r t l a t c h v l 2 / v l 3 v l 1 / v s s k e y i n p u t c o n t r o l k e y - o n w a k e u p i n t e r r u p t i n p u t s e g m e n t d a t a s e g m e n t o u t p u t d i s a b l e b i t d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h l c d p o w e r i n p u t ( v l 1 , v l 2 ) o n l y f o r p 2 6 , p 2 7 v l 2 / v l 3 v l 1 / v s s s e g m e n t d a t a s e g m e n t o u t p u t d i s a b l e b i t segment output disable bit ( 2 ) p o r t s p 0 4 C p 0 7 , p 1 , p 2 d i r e c t i o n r e g i s t e r serial i/o mode selection bit serial i/o enable bit s rdy output enable bit (5) port p3 2 p 3 2 / t x d 2 p - c h a n n e l o u t p u t d i s a b l e b i t s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t (6) port p3 3 s e r i a l i / o e n a b l e b i t r e c e i v e e n a b l e b i t ( 4 ) p o r t p 3 1 serial i/o synchronous clock selection bit serial i/o enable bit d i r e c t i o n r e g i s t e r
16 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 13 port block diagram (2) a n a l o g i n p u t p i n s e l e c t i o n b i t a-d conversion input d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r pull-up control data bus serial i/o clock output port latch direction register pull-up control serial i/o clock input k e y - o n w a k e u p i n t e r r u p t i n p u t k e y i n p u t c o n t r o l data bus direction register port latch p u l l - u p c o n t r o l port latch data bus p u l s e o u t p u t m o d e t i m e r x o u t p u t d i r e c t i o n r e g i s t e r pull-up control direction register d a t a b u s serial i/o enable bi t receive enable bi t port latch pull-up control serial i/o input key-on wakeup interrupt input k e y i n p u t c o n t r o l p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l data bus p o r t l a t c h direction register pull-up control analog input pin selection bit a - d c o n v e r s i o n i n p u t d a t a b u s s e r i a l i / o o u t p u t port latch direction register pull-up control k e y - o n w a k e u p i n t e r r u p t i n p u t k e y i n p u t c o n t r o l ( 7 ) p o r t s p 3 4 , p 3 7 , p 5 0 , p 5 1 , p 6 0 ( 9 ) p o r t s p 3 6 , p 5 2 , p 5 3 ( 1 1 ) p o r t s p 4 0 , p 4 1 , p 4 6 , p 4 7 ( 1 3 ) p o r t p 5 5 (14) port p5 6 (12) port p5 4 (8) port p3 5 (10) ports p4 2 C p4 5 c n t r 0 , c n t r 1 i n t e r r u p t i n p u t i n t 0 C i n t 2 i n t e r r u p t i n p u t p o r t / t i m e r o u t p u t s e l e c t i o n t i m e r o u t p u t / p w m o u t p u t t i m e r o u t p u t / s y s t e m c l o c k o u t p u t o s c i l l a t i o n o u t p u t c o n t r o l b i t / r e a l t i m e c o n t r o l b i t o s c i l l a t i o n o u t p u t / d a t a f o r r e a l t i m e p o r t s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t p 5 5 / t x d 1 p - c h a n n e l o u t p u t d i s a b l e b i t
17 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 14 port block diagram (3) v l3 v l2 v l1 v ss ( 1 5 ) p o r t p 5 7 s e r i a l i / o r e a d y o u t p u t data bus p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l k e y - o n w a k e u p i n t e r r u p t i n p u t key input contro l x c o s c i l l a t i o n e n a b l e d port p6 1 oscillator xc oscillation enabled (17) port p6 2 d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r x c o s c i l l a t i o n e n a b l e d + p u l l - u p c o n t r o l ( 1 7 ) c o m 0 C c o m 3 ( 1 6 ) p o r t p 6 1 data bus port latch direction register x c o s c i l l a t i o n e n a b l e d xc oscillation enabled + pull-up control sub-clock generation circuit input s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s r d y o u t p u t e n a b l e b i t gate input signal of each gate depends on the duty ratio and bias values.
18 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts interrupts occur by nineteen sources: six external, twelve internal, and one software. interrupt control each interrupt except the brk instruction interrupt have both an in- terrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding inter- rupt request and enable bits are 1 and the interrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt re- quest bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. interrupt operation by acceptance of an interrupt, the following operations are automati- cally performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. the interrupt jump destination address is read from the vector table into the program counter. notes on interrupts when the active edge of an external interrupt (int 0 C int 2 , cntr 0 or cntr 1 ) is set or an interrupt source where several interrupt source is assigned to the same vector address is switched, the correspond- ing interrupt request bit may also be set. therefore, take following sequence: (1) disable the interrupt. (2) set the interrupt edge selection register (timer x control reg- ister for cntr 0 , timer y mode register for cntr 1 ). (3) clear the set interrupt request bit to 0. (4) enable the interrupt. interrupt source reset (note 2) int 0 int 1 int 2 key input (key-on wakeup) serial i/o1 receive serial i/o1 transmit serial i/o2 receive serial i/o2 transmit timer x timer 1 timer 2 timer 3 timer 4 cntr 0 timer y cntr 1 a-d conversion brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at falling of ports p0 0 C p0 3 , p5 4 C p5 7 input logical level and at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or transmit buffer is empty at completion of serial i/o2 data receive at completion of serial i/o2 transmit shift or transmit buffer is empty at timer x underflow at timer 1 underflow at timer 2 underflow at timer 3 underflow at timer 4 underflow at detection of either rising or falling edge of cntr 0 input at timer y underflow at detection of either rising or falling edge of cntr 1 input at completion of a-d conversion at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when int 2 interrupt is selected external interrupt (active edge selectable) valid when key input interrupt is selected external interrupt (falling valid) valid only when serial i/o1 is selected valid only when serial i/o1 is selected valid only when serial i/o2 is selected valid only when serial i/o2 is selected valid only when timer 1 interrupt is selected valid only when timer 2 interrupt is selected external interrupt (active edge selectable) external interrupt (active edge selectable) valid when a-d conversion interrupt is se- lected non-maskable software interrupt low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 7 interrupt vector addresses and priority remarks
19 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 15 interrupt control fig. 16 structure of interrupt-related registers interrupt request bit interrupt enable bit interrupt disable flag (i) brk instruction reset interrupt request b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 2 /key input interrupt switch bit timer y/cntr 1 interrupt switch bit not used (return 0 when read) (do not write to 1 ) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit int 2 interrupt request bit key input interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit serial i/o2 receive interrupt request bit serial i/o2 transmit interrupt request bit timer x interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit key input interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit serial i/o2 receive interrupt enable bit serial i/o2 transmit interrupt enable bit timer x interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 timer 1 interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit timer 4 interrupt request bit cntr 0 interrupt request bit timer y interrupt request bit cntr 1 interrupt request bit ad conversion interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 timer 1 interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit timer 4 interrupt enable bit cntr 0 interrupt enable bit timer y interrupt enable bit cntr 1 interrupt enable bit ad conversion interrupt enable bit not used (returns 0 when read) (do not write to 1 .) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0 0 : int 2 interrupt 1 : key input interrupt 0 : timer y interrupt 1 : cntr 1 interrupt
20 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. key input interrupt (key-on wake-up) a key input interrupt request is generated by detecting the falling edge from any pin of ports p0 0 C p0 3 , p5 4 C p5 7 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 17, where an interrupt request is generated by press- ing one of the keys consisted as an active-low key matrix which in- puts to ports p5 4 C p5 7 . fig. 17 connection example when using key input interrupt and ports p0 and p5 block diagram key input control register = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 key input control register = 1 key input control register = 1 key input control register = 1 key input control register = 1 port p5 4 latch port p5 4 direction register = 0 port p5 5 latch p o r t p 5 5 d i r e c t i o n r e g i s t e r = 0 port p5 6 latch port p5 6 direction register = 0 port p5 7 latch p o r t p 5 7 d i r e c t i o n r e g i s t e r = 0 p o r t p 0 0 l a t c h port p0 0 direction register = 1 port p0 1 latch port p0 1 direction register = 1 port p0 2 latch p o r t p 0 2 d i r e c t i o n r e g i s t e r = 1 p o r t p 0 3 l a t c h port p0 3 direction register = 1 p 5 4 i n p u t p 5 5 i n p u t p5 6 input p 5 7 i n p u t p 0 0 o u t p u t p 0 1 o u t p u t p 0 2 o u t p u t p 0 3 o u t p u t pull register bit 5 = 1 p o r t p 0 i n p u t r e a d i n g c i r c u i t p o r t p x x l l e v e l o u t p u t k e y i n p u t i n t e r r u p t r e q u e s t p o r t p 5 i n p u t r e a d i n g c i r c u i t key input control register = 1 segment output disable register 1 bit 3 = 1 s e g m e n t o u t p u t d i s a b l e r e g i s t e r 1 b i t 2 = 1 segment output disable register 1 bit 1 = 1 segment output disable register 1 bit 0 = 1 ? p-channel transistor for pull-up ? ? cmos output buffer ? ? ? ? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ??
21 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. a key input interrupt is controlled by the key input control register and port direction registers. when the key input interrupt is enabled, set 1 to the key input control register. a key input of any pin of ports p0 0 C p0 3 , p5 4 C p5 7 that have been set to input mode is accepted. fig. 18 structure of key input control register key input control register p5 4 key input control bit p5 5 key input control bit p5 6 key input control bit p5 7 key input control bit p0 0 key input control bit p0 1 key input control bit p0 2 key input control bit p0 3 key input control bit (kic : address 0ff2 16 ) b7 b0 0 : key input interrupt disabled 1 : key input interrupt enabled
22 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. timers 8-bit timer the 38C2 group has four built-in timers : timer 1, timer 2, timer 3, and timer 4. each timer has the 8-bit timer latch. all timers are down-counters. when the timer reaches 00 16 , the contents of the timer latch is reloaded into the timer with the next count pulse. in this mode, the interrupt request bit corresponding to that timer is set to 1. the count can be stopped by setting the stop bit of each timer to 1. frequency divider for timer timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. the count source of the frequency divider is switched to x in or x cin by the cpu mode register. the frequency divider is controlled by the 3-bit register. the division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(x in ) or f(x cin ). timer 1, timer 2 the count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. when f(x cin ) is selected as the count source, counting can be per- formed regardless of x cin oscillation. however, when x cin is stopped, the external pulse input from x cin pin is counted. also, by the timer 12 mode register, each time timer 2 underflows, the signal of which polarity is inverted can be output from p3 6 /t 2out pin. at reset, all bits of the timer 12 mode register are cleared to 0, timer 1 is set to ff 16 , and timer 2 is set to 01 16 . when executing the stp instruction, previously set the wait time at return. timer 3, timer 4 the count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. also, by the timer 34 mode register, each time timer 3 or timer 4 underflows, the signal of which polarity is inverted can be output from p5 2 /t 3out pin or p5 3 /t 4out pin. timer 3 pwm 0 mode, timer 4 pwm 1 mode a pwm rectangular waveform corresponding to the 10-bit accuracy can be output from the p5 2 /pwm 0 pin and p5 3 /pwm 1 pin by set- ting the timer 34 mode register and pwm01 register (refer to figure 21). the n is the value set in the timer 3 (address 0022 16 ) or the timer 4 (address 0023 16 ). the ts is one period of timer 3 or timer 4 count source. one output pulse is the short interval. four output pulses are the long interval. h width of the short interval is obtained by n ? ts. however, in the long interval, h width of output pulse is extended for ts which is set by the pwm01 register (address 0024 16 ).
23 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer 12 mode register (t12m: address 0025 16 ) timer 1 count stop bit 0 : count operation 1 : count stop timer 2 count stop bit 0 : count operation 1 : count stop timer 1 count source selection bits b3 b2 0 0 : frequency divider for timer 1 0 1 : f(x cin ) 1 0 : underflow of timer y 1 1 : not available timer 2 count source selection bits b5 b4 0 0 : underflow of timer 1 0 1 : f(x cin ) 1 0 : frequency divider for timer 2 1 1 : not available timer 2 output selection bit (p3 6 ) 0 : i/o port 1 : timer 2 output t 2out output edge switch bit 0 : start at l output 1 : start at h output timer 34 mode register (t34m: address 0026 16 ) timer 3 count stop bit 0 : count operation 1 : count stop timer 4 count stop bit 0 : count operation 1 : count stop timer 3 count source selection bit 0 : frequency divider for timer 3 1 : underflow of timer 2 timer 4 count source selection bits b4 b3 0 0 : frequency divider for timer 4 0 1 : underflow of timer 3 1 0 : underflow of timer 2 1 1 : not available timer 3 operating mode selection bit 0 : timer mode 1 : pwm mode timer 4 operating mode selection bit 0 : timer mode 1 : pwm mode not used (returns 0 when read) timer 1234 mode register (t1234m: address 0ff3 16 ) t 3out output edge switch bit 0 : start at l output 1 : start at h output t 4out output edge switch bit 0 : start at l output 1 : start at h output timer 3 output selection bit (p5 2 ) 0 : i/o port 1 : timer 3 output timer 4 output selection bit (p5 3 ) 0 : i/o port 1 : timer 4 output timer 2 write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only timer 3 write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only timer 4 write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only not used (returns 0 when read) b7 b0 b7 b0 b7 b0 pwm01 register (pwm01: address 0024 16 ) pwm0 set bits b1 b0 0 0 : no extended 0 1 : extended once in four periods 1 0 : extended twice in four periods 1 1 : extended three times in four periods pwm1 set bits b3 b2 0 0 : no extended 0 1 : extended once in four periods 1 0 : extended twice in four periods 1 1 : extended three times in four periods not used (returns 0 when read) timer 12 frequency division selection register (pre12: address 0ff5 16 ) timer 1 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) timer 2 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) not used (returns 0 when read) b7 b0 b7 b0 timer 34 frequency division selection register (pre34: address 0ff6 16 ) timer 3 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) timer 4 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) not used (returns 0 when read) b7 b0 fig. 19 structure of timer related register
24 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 20 block diagram of timers 1, 2, 3 and 4 timer 1 latch (8) t i m e r 1 ( 8 ) t i m e r 1 i n t e r r u p t r e q u e s t t i m e r 2 i n t e r r u p t r e q u e s t t i m e r 3 i n t e r r u p t r e q u e s t x cin d a t a b u s timer 1 count stop bit 10 bit pwm1 circuit 1/ 2 q q s t p 5 3 l a t c h p5 3 /pwm 1 /t 4out 10 bit pwm0 circuit 1/2 q q s t t i m e r 3 o p e r a t i n g m o d e s e l e c t i o n b i t p5 2 latch timer 3 output control bit p5 2 direction register p 5 2 / p w m 0 / t 3 o u t 00 01 c l o c k f o r t i m e r 1 c l o c k f o r t i m e r 2 clock for timer 3 c l o c k f o r t i m e r 4 s y s t e m c l o c k c o n t r o l b i t s f r e q u e n c y d i v i s i o n s e l e c t i o n b i t s ( 3 b i t s f o r e a c h t i m e r ) c l o c k f o r t i m e r 4 c l o c k f o r t i m e r 3 c l o c k f o r t i m e r 2 c l o c k f o r t i m e r 1 12 t h e f o l l o w i n g v a l u e s c a n b e s e l e c t e d t h e c l o c k f o r t i m e r ; 1 / 1 , 1 / 2 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 1 0 2 4 frequency divider 1/2 q q s t t 2out output edge switch bit timer 2 output control bit p3 6 direction register p 3 6 / t 2 o u t / f / ( l e d 6 ) p3 6 latch t i m e r 2 o u t p u t s e l e c t i o n b i t p 3 6 c l o c k o u t p u t c o n t r o l b i t x c i n x i n s y s t e m c l o c k f 10 t i m e r y o u t p u t t i m e r 3 w r i t e c o n t r o l b i t pwm01 register (2) p w m 0 1 r e g i s t e r ( 2 ) timer 2 write control bit t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s timer 2 count source selection bits timer 2 count stop bit timer 3 count source selection bit timer 3 count stop bit t i m e r 1 t i m e r 2 t i m e r 3 t i m e r 4 timer 2 latch (8) t i m e r 2 ( 8 ) timer 3 latch (8) timer 3 (8) t i m e r 4 i n t e r r u p t r e q u e s t t i m e r 4 w r i t e c o n t r o l b i t timer 4 latch (8) t i m e r 4 ( 8 ) timer 4 count source selection bits timer 4 count stop bit t 3out output edge switch bit t i m e r 3 o u t p u t s e l e c t i o n b i t t i m e r 4 o p e r a t i n g m o d e s e l e c t i o n b i t timer 4 output control bit p 5 3 d i r e c t i o n r e g i s t e r t 4 o u t o u t p u t e d g e s w i t c h b i t t i m e r 4 o u t p u t s e l e c t i o n b i t 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 01 1 0 00 1 0 0 1
25 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 21 waveform of pwm01 16-bit timer frequency divider for timer each timer x and timer y have the frequency dividers for the count source. the count source of the frequency divider is switched to x in or x cin by the cpu mode register. the division ratio of each timer can be controlled by the 3-bit register. the division ratio can be se- lected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(x in ) or f(x cin ). timer x the timer x count source can be selected by setting the timer x mode register. when f(x cin ) is selected as the count source, counting can be performed regardless of x cin oscillation. however, when x cin is stopped, the external pulse input from x cin pin is counted. the timer x operates as down-count. when the timer contents reach 0000 16 , an underflow occurs at the next count pulse and the timer latch contents are reloaded. after that, the timer continues count- down. when the timer underflows, the interrupt request bit correspond- ing to the timer x is set to 1 . six operating modes can be selected for timer x by the timer x mode register and timer x control register. (1) timer mode the count source can be selected by setting the timer x mode regis- ter. in this mode, timer x operates as the 18-bit counter by setting the timer x register (extension). (2) pulse output mode pulses of which polarity is inverted each time the timer underflows are output from the t xout pin. except for that, this mode operates just as in the timer mode. when using this mode, set the port sharing the t xout pin to output mode. (3) igbt output mode after dummy output from the t xout pin, count starts with the int 0 pin input as a trigger. in the case that the timer x output edge switch bit is 0 , when the trigger is detected or the timer x underflows, h is output from the t xout pin. when the count value corresponds with the compare register value, the t xout output becomes l . after noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the int 0 signal can use 4 types of delay time by a delay circuit. when using this mode, set the port sharing the int 0 pin to input mode and set the port sharing the t xout pin to output mode. when the timer x output control bit 1 or 2 of the timer x control reg- ister is set to 1 , the timer x count stop bit is fixed to 1 forcibly by the interrupt signal of int 1 or int 2 . and then, by stopping the timer x counting, the t xout output can be fixed to the signal output at that time. do not write 1 to the timer x register (extension) when using the igbt output mode. (4) pwm mode igbt dummy output, an external trigger with the int 0 pin and output control with pins int 1 and int 2 are not used. except for those, this mode operates just as in the igbt output mode. the period of pwm waveform is specified by the timer x set value. in the case that the timer x output edge switch bit is 0 , the h interval is specified by the compare register set value. when using this mode, set the port sharing the t xout pin to output mode. do not write 1 to the timer x register (extension) when using the pwm mode. o u t p u t w a v e f o r m o f t i m e r 3 p w m 0 o r t i m e r 4 p w m 1 256 ? t s 256 ? t s 256 ? t s 256 ? t s n ? t s n ? ts n ? t s n ? t s n ? t s n ? t s n ? t s n ? ts n ? t s n ? t s p w m 0 1 r e g i s t e r = 0 0 2 n: setting value of timer 3 or timer 4 ts: one period of timer 3 count source or timer 4 count source pwm01 register (address 0024 16 ) : 2-bit value corresponding to pwm0 or pwm1 (n+1) ? ts (n+1) ? ts (n+1) ? ts (n+1) ? ts ( n + 1 ) ? t s ( n + 1 ) ? t s p w m 0 1 r e g i s t e r = 0 1 2 p w m 0 1 r e g i s t e r = 1 0 2 p w m 0 1 r e g i s t e r = 1 1 2 s h o r t i n t e r v a l short interval short interval s h o r t i n t e r v a l 4 ? 256 ? t s long interval
26 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 22 waveform of pwm/igbt (5) event counter mode the timer counts signals input through the cntr 0 pin. in this mode, timer x operates as the 18-bit counter by setting the timer x register (extension). when using this mode, set the port sharing the cntr 0 pin to input mode. in this mode, the window control can be performed by the timer 1 underflow. when the bit 5 (data for control of event counter window) of the timer x mode register is set to 1 , counting is stopped at the next timer 1 underflow. when the bit is set to 0 , counting is re- started at the next timer 1 underflow. (6) pulse width measurement mode in this mode, the count source is the output of frequency divider for timer. in this mode, timer x operates as the 18-bit counter by setting the timer x register (extension). when the bit 6 of the cntr 0 active edge switch bits is 0 , counting is executed during the h interval of cntr 0 pin input. when the bit is 1 , counting is executed during the l interval of cntr 0 pin input. when using this mode, set the port sharing the cntr 0 pin to input mode. notes on timer x (1) write order to timer x ? in the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer x register (extension), the timer x register (low-order), the timer x register (high-order). do not write to only one of them. when the above mode is set and timer x operates as the 16-bit counter, if the timer x register (extension) is never set after reset is released, setting the timer x register (extension) is not required. in this case, write the timer x register (low-order) first and the timer x register (high-order). however, once writing to the timer x register is executed, note that the value is retained to the reload latch. ? in the igbt and pwm modes, do not write 1 to the timer x register (extension). also, when 1 is already written to the timer x register, be sure to write 0 to the register before using. write to the following registers in the order as shown below; the compare register (high- and low-order), the timer x register (extension), the timer x register (low-order), the timer x register (high-order). it is possible to use whichever order to write to the compare regis- ter (high- and low-order). however, write both the compare register and the timer x register at the same time. (2) read order to timer x ? in all modes, read the following registers in the order as shown below; the timer x register (extension), the timer x register (high-order), the timer x register (low-order). when reading the timer x register (extension) is not required, read the timer x register (high-order) first and the timer x register (low- order). read order to the compare register is not specified. ? if reading to the timer x register during write operation or writing to it during read operation is performed, normal operation will not be performed. (3) write to timer x ? when writing a value to the timer x address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. normally, when writing a value to the timer x address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. when writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. in this time, counting is stopped during writing to the high-order reload latch. ? do not switch the timer count source during timer count operation. stop the timer count before switching it. t s timer x count source t i m e r x p w m m o d e i g b t m o d e ( n - m + 1 ) ? t sm ? t s ( n + 1 ) ? t s w h e n t h e t i m e r x s e t t i n g v a l u e = n a n d t h e c o m p a r e r e g i s t e r s e t t i n g v a l u e = m , t h e f o l l o w i n g p w m w a v e f o r m i s o u t p u t ; d u t y : ( n - m + 1 ) / ( n + 1 ) p e r i o d : ( n + 1 ) ? t s ( t s : p e r i o d o f t i m e r x c o u n t s o u r c e )
27 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. (4) set of timer x mode register set the write control bit of the timer x mode register to 1 (write to the latch only) when setting the igbt output and pwm modes. output waveform simultaneously reflects the contents of both regis- ters at the next underflow after writing to the timer x register (high- order). (5) output control function of timer x when using the output control function (int 1 and int 2 ) in the igbt output mode, set the levels of int 1 and int 2 to h in the falling edge active or to l in the rising edge active before switching to the igbt output mode. (6) note on switch of cntr 0 active edge ? when the cntr 0 active edge switch bits are set, at the same time, the interrupt active edge is also affected. ? when the pulse width is measured, set the bit 7 of the cntr 0 ac- tive edge switch bits to 0 . timer y timer y is a 16-bit timer. the timer y count source can be selected by setting the timer y mode register. when f(x cin ) is selected as the count source, counting can be performed regardless of x cin oscillation. however, when x cin is stopped, the external pulse input from x cin pin is counted. four operating modes can be selected for timer y by the timer y mode register. also, the real time port can be controlled. (1) timer mode the timer y count source can be selected by setting the timer y mode register. (2) period measurement mode the interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting. except for that, this mode operates just as in the timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input is found by cntr 1 inter- rupt. when using this mode, set the port sharing the cntr 1 pin to input mode. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for that, this mode operates just as in the timer mode. when using this mode, set the port sharing the cntr 1 pin to input mode. (4) pulse width hl continuously measurement mode the interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for that, this mode operates just as in the period measurement mode. when using this mode, set the port sharing the cntr 1 pin to input mode. notes on timer y cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. timer y read/write control ? when reading from/writing to timer y, read from/write to both the high-order and low-order bytes of timer y. when the value is read, read the high-order bytes first and the low-order bytes next. when the value is written, write the low-order bytes first and the high- order bytes next. if reading from the timer y register during write operation or writing to it during read operation is performed, normal operation will not be performed. ? when writing a value to the timer y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. normally, when writing a value to the timer y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. when writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. in this time, counting is stopped during writing to the high-order reload latch. ? do not switch the timer count source during timer count operation. stop the timer count before switching it. real time port control when the real time port function is valid, data for the real time port is output from ports p4 7 and p4 6 each time the timer y underflows. (however, if the real time port control bit is changed from 0 to 1 after the data for real time port is set, data is output independent of the timer y operation.) when the data for the real time port is changed while the real time port function is valid, the changed data is output at the next underflow of timer y. before using this function, set the cor- responding port direction registers to output mode.
28 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 23 structure of timer x, y related registers timer x mode register (txm: address 002f 16 ) timer x operating mode bits b2 b1 b0 0 0 0 : timer mode 0 0 1 : pulse output mode 0 1 0 : igbt output mode 0 1 1 : pwm mode 1 0 0 : event counter mode 1 0 1 : pulse width measurement mode timer x write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only timer x count source selection bit 0 : frequency divider output 1 : f(x cin ) data for control of event counter window 0 : event count enabled 1 : event count disabled timer x count stop bit 0 : count operation 1 : count stop timer x output selection bit (p3 5 ) 0 : i/o port 1 : timer x output b7 b0 timer x control register (txcon: address 0ff4 16 ) noise filter sampling clock selection bit 0 : f(x in )/2 1 : f(x in )/4 external trigger delay time selection bits b2 b1 0 0 : not delayed 0 1 : (4/f(x in )) s 1 0 : (8/f(x in )) s 1 1 : (16/f(x in )) s timer x output control bit 1 (p5 1 ) 0 : not used 1 : int 1 interrupt used timer x output control bit 2 (p3 4 ) 0 : not used 1 : int 2 interrupt used timer x output edge switch bit 0 : start at l output 1 : start at h output cntr 0 active edge switch bits b7 b6 0 0 : count at rising edge in event counter mode falling edge active for cntr 0 interrupt measure h pulse width in pulse width measurement mode 0 1 : count at falling edge in event counter mode rising edge active for cntr 0 interrupt measure l pulse width in pulse width measurement mode 1 0 : count at both edges in event counter mode both edges active for cntr 0 interrupt 1 1 : count at both edges in event counter mode both edges active for cntr 0 interrupt b7 b0 timer xy frequency division selection register (prexy: address 0ff7 16 ) timer x frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) timer y frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ? f(x in ) or 1/16 ? f(x cin ) 0 0 1 : 1/1 ? f(x in ) or 1/1 ? f(x cin ) 0 1 0 : 1/2 ? f(x in ) or 1/2 ? f(x cin ) 0 1 1 : 1/32 ? f(x in ) or 1/32 ? f(x cin ) 1 0 0 : 1/64 ? f(x in ) or 1/64 ? f(x cin ) 1 0 1 : 1/128 ? f(x in ) or 1/128 ? f(x cin ) 1 1 0 : 1/256 ? f(x in ) or 1/256 ? f(x cin ) 1 1 1 : 1/1024 ? f(x in ) or 1/1024 ? f(x cin ) not used (returns 0 when read) b7 b0 timer y mode register (tym: address 0030 16 ) real time port control bit 0 : real time port function invalid 1 : real time port functin valid p4 6 data for real time port p4 7 data for real time port timer y count source selection bit 0 : frequency divider output 1 : f(x cin ) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuous measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure falling period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure rising period in period measurement mode rising edge active for cntr 1 interrupt timer y count stop bit 0 : count operation 1 : count stop b7 b0 timer y mode register 2 (tym2: address 0ffb 16 ) timer y write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only not used (returns 0 when read) b7 b0
29 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 24 block diagram of timer x, y real time port control bit real time port control bit q d latch q d l a t c h p4 7 direction register p4 7 latch p4 7 data for real time port p4 6 direction register p4 6 latch p4 6 data for real time port 1 timer y (low-order) latch (8) 0 cntr 1 active edge switch bit 10 p 4 7 / r t p 1 / a n 7 p4 6 /rtp 0 /an 6 p6 0 /cntr 1 falling edge detection period measurement mode t i m e r y i n t e r r u p t r e q u e s t pulse width hl continuous measurement mode timer y operating mode bits c n t r 1 i n t e r r u p t r e q u e s t rising edge detection count source selection bit x c i n 1 clock for timer y d a t a b u s 1 / 2 1 / 4 f r e q u e n c y d i v i d e r n o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t 1 0 t i m e r x i n t e r r u p t r e q u e s t equal 000 001 010 011 101 p u l s e w i d t h m e a s u r e m e n t m o d e timer x count stop bit compare register (low-order)(8) compare register (high-order)(8) output selection bit p3 5 latch p3 5 direction register p3 5 /t xout /(led 5 ) p 5 1 / i n t 1 p 3 4 / i n t 2 / ( l e d 4 ) s q q t r t xout edge switch bit s 0 1 q q t s pulse output mode c n t r 0 a c t i v e e d g e s w i t c h b i t s t i m e r x o p e r a t i n g m o d e b i t s cntr 0 interrupt request 1 0 0 e x t e n d l a t c h ( 2 ) e x t e n d c o u n t e r ( 2 ) t i m e r x w r i t e c o n t r o l b i t t i m e r 1 i n t e r r u p t d q l a t c h data for control of event counter window p 3 7 / c n t r 0 / ( l e d 7 ) p 5 0 / i n t 0 0 00 01 10 11 8/f(x in ) 16/f(x in ) n o i s e f i l t e r ( 4 t i m e s s a m e l e v e l s j u d g m e n t ) i n t 0 i n t e r r u p t r e q u e s t count source selection bit xc in c l o c k f o r t i m e r x sy s t e m c l o c k c o n t r o l b i t s 3 c l o c k f o r t i m e r y x i n r e a l t i m e p o r t c o n t r o l b i t timer y mode register write signal timer y (low-order)(8) x c i n x i n f r e q u e n c y d i v i d e r igbt output mode pwm mode timer y operating mode bits timer x frequency division selection bit timer y frequency division selection bit 3 b o t h e d g e s d e t e c t i o n 00 0 1 1 0 1 1 edge detection t xout output control bit 1 t x o u t o u t p u t c o n t r o l b i t 2 timer x operating mode bits 0 1 0 00 , 01 , 11 1 0 1 0 1 0 00 , 01 , 10 1 1 0 timer y write control bit t i m e r y c o u n t s t o p b i t 000 001 011 100 101 timer x operating mode bits 0 1 0 delay circuit timer y (high-order) latch (8) timer y (high-order)(8) timer x (low-order) latch (8) timer x (low-order)(8) timer x (high-order) latch (8) t i m e r x ( h i g h - o r d e r ) ( 8 ) t h e f o l l o w i n g v a l u e s c a n b e s e l e c t e d t h e c l o c k f o r t i m e r ; 1 / 1 , 1 / 2 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 1 0 2 4 1 0
30 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. serial i/o the 38C2 group has built-in two 8-bit serial i/o. serial i/o can be used as either clock synchronous or asynchronous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o control register to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 25 block diagram of clock synchronous serial i/o fig. 26 operation of clock synchronous serial i/o function 1/4 1/4 f/f p5 6 /s clk1 [p3 1 /s clk2 ] serial i/o status register serial i/o control register p5 7 /s rdy1 [p3 0 /s rdy2 ] p5 4 /r x d 1 [p3 3 /r x d 2 ] p5 5 /t x d 1 [p3 2 /t x d 2 ] f(x in ) receive buffer register address 001c 16 [address 001e 16 ] receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 0fe2 16 [address 0fe5 16 ] brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 001c 16 [address 001e 16 ] shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 001d 16 [address 001f 16 ] data bus address 0fe0 16 [address 0fe3 16 ] transmit shift register (f(x cin ) in low-speed mode) [ ] : for serial i/o2 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy
31 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clear- ing the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift regis- ter cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the re- ceive buffer register. the transmit buffer register can also hold the next data to be trans- mitted, and the receive buffer register can hold a character while the next character is being received. fig. 27 block diagram of uart serial i/o f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) st/sp/pa generator transmit buffer register data bus transmit shift register transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) st detector sp detector uart control register address 0fe1 16 [address 0fe4 16 ] character length selection bit brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register serial i/o status register (f(x cin ) in low-speed mode) p5 6 /s clk1 [p3 1 /s clk2 ] p5 4 /r x d 1 [p3 3 /r x d 2 ] p5 5 /t x d 1 [p3 2 /t x d 2 ] address 001c 16 [address 001e 16 ] address 0fe2 16 [address 0fe5 16 ] address 001c 16 [address 001e 16 ] address 001d 16 [address 001f 16 ] address 0fe0 16 [address 0fe3 16 ] [ ] : for serial i/o2 fig. 28 operation of uart serial i/o function tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? serial output t x d serial input r x d receive buffer read signal
32 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. [transmit buffer register/receive buffer reg- ister (tb/rb)] the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o status register (sio1sts, sio2sts)] the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is trans- ferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o control register (sio1con, sio2con)] the serial i/o control register consists of eight control bits for the serial i/o function. [uart control register (uart1con, uart2con)] the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the p5 5 /t x d 1 [p3 2 /txd 2 ] pin. [baud rate generator (brg1, brg2)] the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
33 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 29 structure of serial i/o related registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o status register serial i/o control register b0 b0 brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p5 7 [p3 0 ] pin operates as ordinary i/o pin 1: p5 7 [p3 0 ] pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p5 4 [p3 0 ] to p5 7 [p3 3 ] operate as ordinary i/o pins) 1: serial i/o enabled (pins p5 4 [p3 0 ] to p5 7 [p3 3 ] operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p5 5 /txd 1 [p3 2 /txd 2 ] p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (sio1sts : address 001d 16 ) [sio2sts : address 001f 16 ] (sio1con : address 0fe0 16 ) [sio2con : address 0fe3 16 ] (uart1con : address 0fe1 16 ) [uart2con : address 0fe4 16 ] ( ) : for serial i/o1 [ ] : for serial i/o2
34 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter the 38C2 group has a 10-bit a-d converter. the a-d converter per- forms successive approximation conversion. [a-d conversion register (adl, adh)] one of these registers is a high-order register, and the other is a low- order register. the high-order 8 bits of a conversion result is stored in the a-d conversion register (high-order) (address 001b 16 ), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the a-d conversion register (low-order) (address 001a 16 ). during a-d conversion, do not read these registers. also, the connection between the resistor ladder and reference volt- age input pin (v ref ) can be controlled by the v ref input switch bit (bit 0 of address 001a 16 ). when 1 is written to this bit, the resistor ladder is always connected to v ref . when 0 is written to this bit, the resistor ladder is disconnected from v ref except during the a-d conversion. [a-d control register (adcon)] this register controls a-d converter. bits 2 to 0 are analog input pin selection bits. bit 3 is an ad conversion completion bit and 0 during a- d conversion. this bit is set to 1 upon completion of a-d conversion. a-d conversion is started by setting 0 in this bit. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref , and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p4 7 /an 7 C p4 0 / an 0 and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad conver- sion interrupt request bit to 1. fig. 31 block diagram of a-d converter fig. 30 structure of a-d control register data bus av ss a-d interrupt request b7 b0 3 p4 0 /o out0 /an 0 p4 1 /o out1 /an 1 p4 2 /an 2 p4 3 /an 3 p4 4 /an 4 p4 5 /an 5 p4 6 /an 6 p4 7 /an 7 a-d control register channel selector comparator a-d control circuit a-d conversion register (h) a-d conversion register (l) (address 001b 16 ) (address 001a 16 ) resistor ladder v ref analog input pin selection bits b2 b1 b0 0 0 0: p4 0 /an 0 0 0 1: p4 1 /an 1 0 1 0: p4 2 /an 2 0 1 1: p4 3 /an 3 1 0 0: p4 4 /an 4 1 0 1: p4 5 /an 5 1 1 0: p4 6 /an 6 1 1 1: p4 7 /an 7 ad conversion completion bit 0: conversion in progress 1: conversion completed ad conversion clock selection bits b5 b4 0 0: frequency not divided 0 1: frequency divided by 2 1 0: frequency divided by 4 1 1: frequency divided by 8 10-bit or 8-bit conversion switch bit 0: 10-bit ad 1: 8-bit ad booster selection bit 0: booster not used 1: booster used a-d control register (adcon: address 0019 16 ) b7 b0 10-bit reading (read address 001b 16 before 001a 16 ) a-d conversion register 1 (address 001b 16 ) a-d conversion register 2 (address 001a 16 ) 8-bit reading (read only address 001b 16 ) (address 001b 16 ) b0 b7 b0 b1 * v ref input switch bit b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 * (high-order) (low-order) note : the bit 5 to bit 1 of address 001a 16 becomes 0 at reading. also, bit 0 is undefined at reading. 1: on 0: on only during a-d conversion
35 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. lcd drive control circuit the 38C2 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output disable register ? lcd mode register ? selector ? timing controller ? common driver ? segment driver ? bias control circuit a maximum of 24 segment output pins and 4 common output pins can be used. up to 96 pixels can be controlled for an lcd display. when the lcd enable bit is set to 1 after data is set in the lcd mode register, the fig. 32 structure of lcd related registers segment output disable register, and the lcd display ram, the lcd drive control circuit starts reading the display data automatically, per- forms the bias control and the duty ratio control, and displays the data on the lcd panel. table 8 maximum number of display pixels at each duty ratio duty ratio 2 3 4 maximum number of display pixels 48 dots or 8 segment lcd 6 digits 72 dots or 8 segment lcd 9 digits 96 dots or 8 segment lcd 12 digits segment output disable bit 0 0 : segment output seg 0 1 : output port p0 0 segment output disable bit 1 0 : segment output seg 1 1 : output port p0 1 segment output disable bit 2 0 : segment output seg 2 1 : output port p0 2 segment output disable bit 3 0 : segment output seg 3 1 : output port p0 3 segment output disable bit 4 0 : segment output seg 4 1 : output port p0 4 segment output disable bit 5 0 : segment output seg 5 1 : output port p0 5 segment output disable bit 6 0 : segment output seg 6 1 : output port p0 6 segment output disable bit 7 0 : segment output seg 7 1 : output port p0 7 segment output disable register 0 (seg0 : address 0ff8 16 ) b7 b0 lcd mode register (lm : address 0039 16 ) duty ratio selection bits b1 b0 0 0 : not used 0 1 : 2 (use com 0 ,com 1 ) 1 0 : 3 (use com 0 C com 2 ) 1 1 : 4 (use com 0 C com 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on lcd drive timing selection bit 0 : type a 1 : type b lcd circuit divider division ratio selection bits b6 b5 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 (f(x cin )/8192 in low-speed mode) note : lcdck is a clock for an lcd timing controller. b7 b0 segment output disable bit 8 0 : segment output seg 8 1 : output port p1 0 segment output disable bit 9 0 : segment output seg 9 1 : output port p1 1 segment output disable bit 10 0 : segment output seg 10 1 : output port p1 2 segment output disable bit 11 0 : segment output seg 11 1 : output port p1 3 segment output disable bit 12 0 : segment output seg 12 1 : output port p1 4 segment output disable bit 13 0 : segment output seg 13 1 : output port p1 5 segment output disable bit 14 0 : segment output seg 14 1 : output port p1 6 segment output disable bit 15 0 : segment output seg 15 1 : output port p1 7 segment output disable register 1 (seg1 : address 0ff9 16 ) b7 b0 segment output disable bit 16 0 : output port p2 0 1 : segment output seg 16 segment output disable bit 17 0 : output port p2 1 1 : segment output seg 17 segment output disable bit 18 0 : output port p2 2 1 : segment output seg 18 segment output disable bit 19 0 : output port p2 3 1 : segment output seg 19 segment output disable bit 20 0 : output port p2 4 1 : segment output seg 20 segment output disable bit 21 0 : output port p2 5 1 : segment output seg 21 segment output disable bit 22 0 : output port p2 6 1 : segment output seg 22 segment output disable bit 23 0 : output port p2 7 1 : segment output seg 23 segment output disable register 2 (seg2 : address 0ffa 16 ) b7 b0 note : only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register.
36 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 33 block diagram of lcd controller/driver f ( x c i n ) / 3 2 f ( x i n ) / 8 1 9 2 l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t c o m 0 c o m 1 c o m 2 c o m 3 v s s p 2 7 / s e g 2 3 / v l 2 v l 3 p 2 6 / s e g 2 2 / v l 1 p 0 3 / s e g 3 p 0 2 / s e g 2 p 0 1 / s e g 1 p 0 0 / s e g 0 p 2 0 / s e g 1 6 0 1 l c d c k 2 2 5 p 2 7 / v l 2 s e g 2 3 / p 2 6 / v l 1 s e g 2 2 / d a t a b u s t i m i n g c o n t r o l l e r l c d d i v i d e r ( f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) c o m m o n d r i v e r b i a s c o n t r o l a d d r e s s 0 0 4 0 1 6 a d d r e s s 0 0 4 1 1 6 l c d c k c o u n t s o u r c e s e l e c t i o n b i t l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s b i a s c o n t r o l b i t l c d e n a b l e b i t d u t y r a t i o s e l e c t i o n b i t s s e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r l c d d i s p l a y r a m a d d r e s s 0 0 4 c 1 6 s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r s e l e c t o r s e l e c t o r s e g m e n t d r i v e r s e g m e n t d r i v e r l c d p o w e r c o n t r o l r e g i s t e r
37 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. duty ratio 2 3 4 voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd bias control and applied voltage to lcd power input pins when the voltage is applied from the lcd power input pins (v l1 C v l3 ), set the vl pin input selection bit (bit 5 of the lcd power control register) and v l3 connection bit (bit 6 of lcd power control register) to 1 , apply the voltage value shown in table 9 according to the bias value. in this case, seg 22 pin and seg 23 pin cannot be used. select a bias value by the bias control bit (bit 2 of the lcd mode register). fig. 34 example of circuit at each bias (at external power input) table 9 bias control and applied voltage to v l1 ? l3 bias value 1/3 bias 1/2 bias note : v lcd is the maximum value of supplied voltage for the lcd panel. table 10 duty ratio control and common pins used note: unused common pin outputs the unselected waveform. common pins used com 0 , com 1 com 0 C com 2 com 0 C com 3 bit 1 0 1 1 bit 0 1 0 1 duty ratio selection bit common pin and duty ratio control the common pins (com 0 C com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). when reset is released, v cc voltage is out- put from the common pin. segment signal output pin the segment signal output pins (seg 0 C seg 23 ) are shared with ports p0 C p2. when these pins are used as the segment signal output pins, set the direction registers of the corresponding pins to 1 , and clear the segment output disable register to 0 . also, these pins are set to the input port after reset, the v cc voltage is output by the pull-up resistor. v l3 v l2 v l1 r 4 r5 r4 = r5 c o n t r a s t a d j u s t 1/2 bias v l 3 v l 2 v l 1 c o n t r a s t a d j u s t r1 r 2 r3 r 1 = r 2 = r 3 1 / 3 b i a s
38 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. lcd power circuit the lcd power circuit has the dividing resistor for lcd power which can be connected/disconnected with the lcd power control register. fig. 35 structure of lcd power control register dividing resistor for lcd power control bit (lcdron) 0 : internal dividing resistor disconnected from lcd power circuit 1 : internal dividing resistor connected to lcd power circuit dividing resistor for lcd power selection bits (rsel) b3 b2 1 0 : larger resistor 0 1 : 0 0 : 1 1 : smaller resistor not used (return 0 when read) (do not write to 1 ) vl pin input selection bit (vlsel) 0 : input invalid 1 : vl input function valid v l3 connection bit 0 : connect lcd internal v l3 to v cc 1 : connect lcd internal v l3 to v l3 pin not used (return 0 when read) (do not write to 1 ) lcd power control register (vlcon : address 0038 16 ) b7 b0 fig. 36 vl block diagram v l 3 p 2 7 / s e g 2 3 / v l 2 p 2 6 / s e g 2 2 / v l 1 vcc l c d m o d e r e g i s t e r ( b i t 2 ) l c d p o w e r c o n t r o l r e g i s t e r ( b i t 5 ) lcd power control register (bit 0) d i v i d i n g r e s i s t o r f o r l c d p o w e r l c d p o w e r c o n t r o l r e g i s t e r ( b i t s 2 a n d 1 ) lcd power control register (bit 6) l c d i n t e r n a l v l 3 l c d i n t e r n a l v l 2 l c d i n t e r n a l v l 1
39 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 37 lcd display ram map lcd display ram the 12-byte area of address 0040 16 to 004b 16 is the designated ram for the lcd display. when 1 is written to these addresses, the corresponding segments of the lcd display panel are turned on. lcd drive timing for the lcd drive timing, type a or type b can be selected. the lcd drive timing is selected by the timing selection bit (bit 4 of lcd mode register). type a is selected by setting the lcd drive timing selection bit to 0 , type b is selected by setting the bit to 1 . type a is selected after reset. the lcdck timing frequency (lcd drive timing) is generated inter- nally and the frame frequency can be determined with the following equation; note (1) when the stp instruction is executed, the following bits are cleared to 0 ; ? lcd enable bit (bit 3 of lcd mode register) ? bits other than bit 6 of the lcd power control register. (2) when the voltage is applied to v l1 to v l3 by using the external resistor, write 10 2 to dividing resistor for lcd power selection bits (rsel) of the lcd power control register (address 38 16 ). c o m 3 c o m 2 c o m 1 c o m 0 bit address 7 6543 21 0 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 seg 1 seg 3 seg 5 seg 7 seg 9 seg 11 seg 13 seg 15 seg 17 seg 19 seg 21 seg 23 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 c o m 3 c o m 2 c o m 1 c o m 0
40 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 38 lcd drive waveform (1/2 bias, type a) 1 / 4 d u t y voltage level v l3 v l2 =v l1 v ss v l3 v ss c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 o f fo n o f fon c o m 3 com 2 com 1 com 0 c o m 3 com 2 com 1 com 0 1 / 3 d u t y v l3 v l2 =v l1 v ss v l3 v ss off o n o noff o no f f 1 / 2 d u t y c o m 0 c o m 1 c o m 2 s e g 0 com 0 c o m 1 s e g 0 v l3 v l2 =v l1 v ss v l3 v ss off o n o f f o n off o n off o n c o m 0 c o m 2 com 1 c o m 0 c o m 2 com 1 com 0 c o m 2 c o m 1 c o m 0 com 1 com 0 c o m 1 com 0 com 1 c o m 0 i n t e r n a l s i g n a l l c d c k t i m i n g lcd lcd l c d
41 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 39 lcd drive waveform (1/3 bias, type a) v l 3 v ss c o m 0 c o m 1 c o m 2 c o m 3 seg 0 c o m 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 c o m 0 c o m 1 com 2 s e g 0 c o m 0 c o m 1 s e g 0 v l 3 v l 2 v s s v l 1 v l 3 v l 2 v ss v l 1 v l 3 v ss v l 3 v l 2 v s s v l1 v l 3 v s s com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 c o m 1 com 0 com 1 com 0 c o m 1 com 0 com 1 com 0 1 / 4 d u t y voltage level o f fon offo n 1 / 3 d u t y off o no noff o noff 1/2 duty off o no f f on o f f o noff o n i n t e r n a l s i g n a l l c d c k t i m i n g lcd l c d l c d
42 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 40 lcd drive waveform (1/2 bias, type b) c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 c o m 0 com 1 c o m 2 s e g 0 c o m 0 c o m 1 s e g 0 v l3 v l2= v l1 v ss c o m 0 c o m 2 c o m 1 com 0 c o m 2 c o m 1 c o m 0 c o m 2 c o m 1 c o m 0 com 1 c o m 0 c o m 1 com 0 c o m 1 c o m 0 1 frame 1 f r a m e 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame v l3 v ss v l3 v ss v l3 v ss v l3 v l2= v l1 v ss v l3 v l2= v l1 v ss 1/4 duty v o l t a g e l e v e l off on off on 1 / 3 d u t y o f f on o no f fono f f 1 / 2 d u t y o f f o no f f o no f f o noff on i n t e r n a l s i g n a l l c d c k t i m i n g l c d l c d lcd
43 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 41 lcd drive waveform (1/3 bias, type b) c o m 0 c o m 1 c o m 2 c o m 3 seg 0 c o m 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 c o m 0 c o m 1 com 2 seg 0 c o m 0 c o m 1 seg 0 v l 3 v l 2 v s s v l 1 v l 3 v l 2 v ss v l 1 v l 3 v l 2 v s s v l1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 c o m 1 com 0 com 1 com 0 c o m 1 c o m 0 com 1 c o m 0 v l 3 v l 2 v ss v l1 v l3 v l 2 v ss v l 1 v l 3 v l 2 v s s v l1 1 f r a m e 1 f r a m e 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 / 4 d u t y v o l t a g e l e v e l off on off on 1 / 3 d u t y o f f o no no f fo no f f 1 / 2 d u t y o f f o no f f on off on o f f o n i n t e r n a l s i g n a l l c d c k t i m i n g l c d lcd l c d
44 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). the watchdog timer consists of an 8-bit counter. initial value of watchdog timer at reset or writing to the watchdog timer control register, each watch- dog timer is set to ff 16 . instructions such as sta, ldm and clb to generate the write signals can be used. the written data in bits 0 to 5 are not valid, and the above values are set. standard operation of watchdog timer the watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watch- dog timer control register. an internal reset occurs at an underflow of the watchdog timer. then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. normally, writing to the watchdog timer control register before an underflow of the watchdog timer is programmed. if writing to the watch- dog control register is not executed, the watchdog timer does not operate. fig. 44 timing diagram of reset output when reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the stp instruction dis- able bit (bit 6), and the count source selection bit (bit 7) are read out. when the stp instruction disable bit is 0 , the stp instruction is valid. the stp instruction is disabled by writing to 1 to this bit. in this time, when the stp instruction is executed, it is handled as the undefined instruction, the internal reset occurs. this bit cannot be cleared to 0 by program. this bit is 0 after reset. the time until the underflow of the watchdog timer control register after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is 0 ) ; ? at through, frequency/2/4/8 mode (f(x in )) = 8 mhz): 32.768 ms ? at low-speed mode (f(x cin ) = 32 khz): 8.19s note the watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. accordingly, do not underflow the watchdog timer in this time. fig. 42 block diagram of watchdog timer fig. 43 structure of watchdog timer control register b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer count source selection bit 0: 1/1024 of system clock 1: 1/4 of system clock watchdog timer h (for read-out of high-order 6 bit) ff 16 is set to watchdog timer by writing to these bits. watchdog timer control register (wdtcon : address 0037 16 ) b7 i n t e r n a l r e s e t s i g n a l watchdog timer detected 32 msec (at f(x in )=8mh z ) f ( x i n ) x in x c i n sy s t e m c l o c k c o n t r o l b i t ( b i t 6 ) 1/1024 u n d e f i n e d i n s t r u c t i o n r e s e t r e s e t i n wait until reset release 1 / 4 d a t a b u s w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c t i o n b i t r e s e t c i r c u i t s t p i n s t r u c t i o n d i s a b l e b i t watchdog timer h (6) internal reset s t p i n s t r u c t i o n watchdog timer l (2) f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . 1 0 0 1
45 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. clock output function a system clock can be output from i/o port p3 6 .the triple function of i/o port, timer 2 output function and system clock output function is performed by the clock output control register (address 0018 16 ) and the timer 2 output selection bit of the timer 12 mode register (address 0025 16 ). in order to output a system clock from i/o port p3 6 , set the timer 2 output selection bit and bit 0 of the clock output control register to 1 . when the clock output function is selected, a clock is output while the direction register of port p3 6 is set to the output mode. p3 6 is switched to the port output or the output (timer 2 output and the clock output) except port at the cycle after the timer 2 output control bit is switched. fig. 46 block diagram of clock output function fig. 45 structure of clock output control register b0 not used (returns 0 when read) p3 6 clock output control bit 0: timer 2 output 1: system clock output clock output control register (ckout : address 0018 16 ) b7 t i m e r 2 l a t c h ( 8 ) t i m e r 2 ( 8 ) 1 / 2 q q s t t 2 o u t o u t p u t e d g e s w i t c h b i t t i m e r 2 o u t p u t c o n t r o l b i t p 3 6 l a t c h t i m e r 2 o u t p u t s e l e c t i o n b i t p 3 6 d i r e c t i o n r e g i s t e r p 3 6 / t 2 o u t / s y s t e m c l o c k p 3 6 c l o c k o u t p u t c o n t r o l b i t b 7 b 0 t i m e r 1 2 m o d e r e g i s t e r ( a d d r e s s 0 0 2 5 1 6 ) t 1 2 m t i m e r 2 o u t p u t s e l e c t i o n b i t 0 : i / o p o r t 1 : t i m e r 2 o u t p u t 0 1 0 1
46 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the quartz-crystal oscillator should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage meets v il spec. when a power source voltage passes v cc (min.). fig. 48 reset sequence fig. 47 reset circuit example v il spec. 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage reset internal reset address data sync x in fffc fffd ad h, ad l ad l ???? x in : about 8000 cycles note reset address from vector table 1: the frequency relation of f(x in ) and f( ) is f(x in ) = 8 ? f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. ad h
47 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 49 internal status at reset ff 16 ff 16 00 16 002a 16 0 0 2 b 1 6 0 0 2 c 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 a 1 6 x: not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. a d d r e s s r e g i s t e r c o n t e n t s a d d r e s s r e g i s t e r c o n t e n t s 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 00 16 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 8 1 6 0 0 0 9 1 6 000a 16 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0018 16 0 0 1 9 1 6 001d 16 0 0 1 f 1 6 0020 16 0 0 2 1 1 6 0022 16 0 0 2 3 1 6 0024 16 0025 16 0 0 2 8 1 6 c o m p a r e r e g i s t e r ( l o w - o r d e r ) p o r t p 0 p o r t p 0 d i r e c t i o n r e g i s t e r p o r t p 1 p o r t p 2 p o r t p 2 d i r e c t i o n r e g i s t e r p o r t p 3 p o r t p 4 p o r t p 4 d i r e c t i o n r e g i s t e r port p5 p o r t p 5 d i r e c t i o n r e g i s t e r p o r t p 6 p o r t p 6 d i r e c t i o n r e g i s t e r clock output control register a-d control register s e r i a l i / o 1 s t a t u s r e g i s t e r timer 2 t i m e r 3 timer 4 pwm01 register t i m e r 1 2 m o d e r e g i s t e r timer 34 mode register c o m p a r e r e g i s t e r ( h i g h - o r d e r ) t i m e r x ( l o w - o r d e r ) timer x (high-order) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) 00 16 0029 16 t i m e r x ( e x t e n s i o n ) (30) ( 3 2 ) (33) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) t i m e r y ( l o w - o r d e r ) t i m e r y ( h i g h - o r d e r ) t i m e r x m o d e r e g i s t e r w a t c h d o g t i m e r c o n t r o l r e g i s t e r l c d p o w e r c o n t r o l r e g i s t e r l c d m o d e r e g i s t e r i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r 0 0 1 6 00 16 00 16 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 f 1 6 0 f e 0 1 6 0 f e 1 1 6 0 f e 3 1 6 0fe4 16 ( 3 9 ) ( 4 0 ) ( 4 3 ) (44) ( 4 5 ) ( 4 6 ) (47) cpu mode register i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 interrupt control register 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 0 0 1 6 0 0 1 6 0 0 1 6 serial i/o2 status register t i m e r 1 ( 3 1 ) fffc 16 contents (ps) ( p c h ) ( p c l ) p r o g r a m c o u n t e r p r o c e s s o r s t a t u s r e g i s t e r f f f d 1 6 c o n t e n t s 1 ? 0039 16 08 16 ff 16 01 16 ff 16 ff 16 00 16 00 16 00 16 ? ? ? ?? ? 00 16 0 0 0 3 1 6 p o r t p 1 d i r e c t i o n r e g i s t e r (4) 0 0 3 e 1 6 ( 4 1 ) ( 4 2 ) 0 0 1 6 0 0 1 6 0 0 3 d 1 6 0 0 1 6 00 16 00 16 0 f f 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 ( 4 8 ) (49) (50) (51) 0 0 1 6 0 0 1 6 0 f f 4 1 6 0ff5 16 0ff6 16 ( 5 2 ) (53) (54) 00 16 0 0 1 6 0 0 1 6 f f 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 ( 5 5 ) (56) ( 5 7 ) f f 1 6 f f 1 6 0ffa 16 0ffb 16 0 f f e 1 6 (58) ( 5 9 ) (60) 0 0 1 6 (61) ( 6 2 ) p o r t p 3 d i r e c t i o n r e g i s t e r 0 0 0 7 1 6 0 0 2 6 1 6 0 0 2 d 1 6 0 0 2 e 1 6 002f 16 100000 0 0 100000 0 0 00 16 ( 3 4 ) timer y mode register 0 0 3 0 1 6 s e r i a l i / o 1 c o n t r o l r e g i s t e r u a r t1 c o n t r o l r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r u a r t 2 c o n t r o l r e g i s t e r o s c i l l a t i o n o u t p u t c o n t r o l r e g i s t e r pull register k e y i n p u t c o n t r o l r e g i s t e r timer 1234 mode register t i m e r x c o n t r o l r e g i s t e r t i m e r 1 2 f r e q u e n c y d i v i s i o n s e l e c t i o n r e g i s t e r t i m e r 3 4 f r e q u e n c y d i v i s i o n s e l e c t i o n r e g i s t e r timer xy frequency division selection register s e g m e n t o u t p u t d i s a b l e r e g i s t e r 0 s e g m e n t o u t p u t d i s a b l e r e g i s t e r 1 segment output disable register 2 t i m e r y m o d e r e g i s t e r 2 f l a s h m e m o r y c o n t r o l r e g i s t e r 00 11 11 1 1 01 00 10 0 0 0 0 1 6 111000 0 0 111000 0 0 1 ? ? ? 0 0 0 0
48 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. clock generating circuit the 38C2 group has two built-in oscillation circuits; main clock x in C x out and sub-clock x cin Cx cout . an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no external resistor is needed between x in and x out since a feedback resistor exists on-chip. how- ever, an external feedback resistor is needed between x cin and x cout . when the clock signal is supplied from external for the main clock, input the signal to x in pin and input the inverted-phase signal of x in to x out pin by the external inverter. when the clock signal is supplied from external for the sub-clock, input the signal to x cin and leave x cout open. immediately after power on, only the x in oscillation circuit starts os- cillating. frequency control (1) frequency/8 mode the system clock is the frequency of x in divided by 8. after reset is released, this mode is selected. (2) frequency/4 mode the system clock is the frequency of x in divided by 4. (3) frequency/2 mode the system clock is the frequency of x in divided by 2. (4) through mode the system clock is the frequency of x in . (5) low-speed mode the system clock is the frequency of x cin divided by 2. in the low- speed mode, the low-power dissipation operation can be performed when the main clock x in is stopped by setting the bit 7 of the cpu mode register to 0. in this case, when main clock x in oscillation is restarted, generate the wait time until the oscillation is stable by pro- gram after the bit 7 of the cpu mode register is set to 1. fig. 50 ceramic resonator circuit fig. 51 external clock input circuit x o u t c i n c o u t c c i n c c o u t r f c x c i n x c o u t x i n x c i n x c o u t x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v c c v s s o p e n v c c v s s e x t e r n a l o s c i l l a t i o n c i r c u i t , o r e x t e r n a l p u l s e notes on clock generating circuit if you switch the mode between through, frequency/2/4, or 8 and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode, set the frequency on condition that f(x in ) > 3f(x cin ). oscillation control (1) stop mode if the stp instruction is executed, the system clock stops at an h level, and main clock and sub-clock oscillators stop. in this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2) before the stp instruction. the frequency divider for timer 1 is used for the timer 1 count source, and the output of timer 1 is forcibly connected to timer 2. in this time, bits 0 to 5 of the timer 12 mode register are cleared to 0 . the values of the timer 12 frequency divider selection register are not changed. set the interrupt enable bits of the timer 1 and timer 2 to disabled ( 0 ) before executing the stp instruction. oscillator restarts when reset occurs or an interrupt request is re- ceived, but the system clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabi- lize. (2) wait mode if the wit instruction is executed, the system clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the system clock restarts at reset or when an interrupt is received. since the oscillator does not stop, nor- mal operation can be started immediately after the clock is restarted.
49 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 52 clock generating circuit block diagram s r q s r q s r q x i n x o u t 1 / 2 1 / 2 1 / 2 1 / 2 p6 1 /x cin p 6 2 / x c o u t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s through mode 01 00 1 1 0 1 0 0 00 1 0 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 , 1 0 , 1 1 01 01,10,11 0 0 10 0 0 , 1 0 0 0 , 1 0 0 1 , 1 1 01,11 wit instruction system clock 00 0 0 , 1 0 , 1 1 0 1 system clock control bits
50 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 53 state transitions of system clock x i n o s c i l l a t i o n , x c i n s t o p c m 7 = 0 , c m 6 = 1 s y s t e m c l o c k : f ( x i n ) c m 5 = 1c m 4 = 1 t h r o u g h m o d e f r e q u e n c y / 2 m o d e s y s t e m c l o c k : f ( x i n ) / 2 c m 5 = 1c m 4 = 0 cm 7 =0 cm 6 = 1 l o w - s p e e d m o d e s y s t e m c l o c k 1 cm 7 = 0 cm 6 = 0 s y s t e m c l o c k = m a i n c l o c k f ( x i n ) r e s e t cm 5 cm 4 : main clock division ratio selection bits 00: x in /8 (frequency/8) 01: x in /4 (frequency/4) 10: x in /2 (frequency/2) 11: x in (through mode) cm 7 cm 6 : system clock control bits 00: x in stop, x cin oscillation, system clock = x cin 01: x in oscillation, x cin stop, system clock = x in 10: x in oscillation, x cin oscillation, system clock = x cin 11: x in oscillation, x cin oscillation, system clock = x in cpu mode register (cpum : address 003b 16 ) b7 b4 1: when the mode is switched from through or frequency/2/4/8 to the low-speed mode, or the opposite is performed, change cm 7 at first, and then, change cm 6 after the oscillation of the changed mode is stabilized. 2: the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: timer and lcd operate in the wait mode. 4: when the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2. n o t e s frequency/4 mode f r e q u e n c y / 8 m o d e s y s t e m c l o c k 1 x in oscillation, x cin oscillation cm 7 =1, cm 6 =1 t h r o u g h m o d e f r e q u e n c y / 2 m o d e frequency/4 mode f r e q u e n c y / 8 m o d e s y s t e m c l o c k
51 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. oscillation external output function the 38C2 group has the oscillation external output function to output the rectangular waveform of the clock obtained by the oscillation cir- cuits from p4 1 and p4 0 . in order to validate the oscillation external output function, set p4 0 or p4 1 , or both to the output mode (set the corresponding direction reg- ister to 1 ). the level of the x cout external output signal becomes h by the p4 0 /p4 1 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0ff0 16 ) in the following states; ? the function to output the signal from the x cout pin externally is selected ? the sub-clock (x cin C x cout ) is in the oscillating or stop mode. likewise, the level of the x out external output signal becomes h by the p4 0 /p4 1 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0ff0 16 ) in the following states; ? the function to output the signal from the x out pin externally is selected ? the main clock (x in C x out ) is in the oscillating or stop mode. fig. 55 block diagram of oscillation output function fig. 54 structure of oscillation output control register oscillation output control register p4 0 /p4 1 oscillation output control bits b1b0 00: p4 1 , p4 0 = normal port 01: p4 1 = normal port, p4 0 = x out 10: p4 1 = normal port, p4 0 = x cout 11: p4 1 = x cout , p4 0 = x out not used (return 0 when read) (do not write to 1 ) (oscout : address 0ff0 16 ) b7 b0 stp instruction s r q x i n x o u t i n t e r r u p t r e q u e s t i n t e r r u p t d i s a b l e f l a g i r e s e t sy s t e m c l o c k c o n t r o l b i t s p6 1 /x cin p6 2 /x cout system clock control bits 01 sy s t e m c l o c k c o n t r o l b i t s p 4 1 / o o u t 1 p 4 0 / o o u t 0 p4 1 direction register p4 0 direction register oscout control p4 1 output latch p4 0 output latch o s c i l l a t i o n o u t p u t s e l e c t i o n c i r c u i t 0 0 , 1 0 , 1 1 0 1 00 , 10 , 11 0 0 0 1 , 1 0 , 1 1 when the signal from the x out pin or x cout pin of the oscillation circuit is input directly to the circuit except this mcu and used, the system operation may be unstabilized. in order to share the oscillation circuit safely, use the clock output from p4 0 and p4 1 by this function for the circuits except this mcu.
52 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction before executing an sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers ? if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ? the timers share the one frequency divider to generate the count source. accordingly, when each timer starts operating, initializing the frequency divider is not executed. therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. also, the count source cannot be checked externally. multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. ? the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the fol- lowing cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o in clock synchronous serial i/o, if the receive side is using an exter- nal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after trans- mission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 250 khz (note) during an a-d conversion. note: when the frequency divided by 2/4/8 is selected by the ad conversion clock selection bits, the above frequency is multi- plied by 2/4/8. also, when the stp instruction is executed dur- ing the a-d conversion, the a-d conversion is stopped imme- diately, the a-d conversion completion bit is set to 1 , and the interrupt request is generated. lcd when the lcd power input pin v l3 is not used, connect it to v cc . instruction execution time the instruction execution time is obtained by multiplying the number of cycles shown in the list of machine instructions by the period of the internal clock .
53 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics absolute maximum ratings table 11 absolute maximum ratings (mask rom version) parameter power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7, p3 0 Cp3 7, p4 0 Cp4 7 , p5 0 Cp5 7, p6 0 Cp6 2 input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in , cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 output voltage com 0 Ccom 3 output voltage p3 0 Cp3 7 , p4 0 Cp4 7, p5 0 Cp5 7 , p6 0 Cp6 2 output voltage x out power dissipation operating temperature storage temperature symbol v cc v i v i v i v i v i v o v o v o v o p d t opr t stg conditions all voltages are based on vss. output transistors are cut off. at output port at segment output ta = 25 c ratings C0.3 to 6.5 C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to 6.5 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 125 unit v v v v v v v v v v v mw c c recommended operating conditions table 12 recommended operating conditions (mask rom version) (vcc = 1.8 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) power source voltage f( ) = 8 mhz f( ) = 2 mhz low-speed mode power source voltage a-d converter reference voltage analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 4 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 2 , p3 5 , p3 6 , p4 0 Cp4 7 , p5 2 , p5 3 , p6 2 h input voltage p0 0 Cp0 3 , p3 1 , p3 3 , p3 4 , p3 7 , p5 0 , p5 1, p5 4 Cp5 7 , p6 0 , p6 1 h input voltage reset h input voltage x in , x cin l input voltage p0 4 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 2 ,p3 5 , p3 6 , p4 0 Cp4 7 , p5 2 , p5 3 , p6 2 l input voltage p0 0 Cp0 3 , p3 1 , p3 3 , p3 4 , p3 7 , p5 0 , p5 1, p5 4 Cp5 7 , p6 0 , p6 1 , cnv ss l input voltage reset l input voltage x in , x cin v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il limits v v v v v v v v v v v v v v v parameter min. 4.0 1.8 1.8 v cc C0.3 av ss 0.7v cc 0.8v cc 0.9v cc 65 ? v cc C99 100 1.5 0 0 0 0 0 typ. 5.0 5.0 5.0 0 0 max. 5.5 5.5 5.5 v cc +0.3 v cc v cc v cc v cc v cc v cc 0.3v cc 0.2v cc 0.2v cc 65 ? v cc C99 100 0.4 symbol unit 2.2 v v cc 5.5 v v cc 2.2 v 2.2 v v cc 5.5 v v cc 2.2 v v cc C
54 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. h total peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 h total peak output current (note 1) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l total peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 l total peak output current (note 1) p4 0 Cp4 7 , p5 0 , p5 1 , p5 4 Cp5 7 , p6 0 Cp6 2 l total peak output current (note 1) p3 0 Cp3 7 , p5 2 , p5 3 h total average output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 h total average output current (note 1) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l total average output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 l total average output current (note 1) p4 0 Cp4 7 , p5 0 , p5 1 , p5 4 Cp5 7 , p6 0 Cp6 2 l total average output current (note 1) p3 0 Cp3 7 , p5 2 , p5 3 h peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 h peak output current (note 2) p3 0 Cp3 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 l peak output current (note 2) p4 0 Cp4 7 , p5 0 , p5 1 , p5 4 Cp5 7 , p6 0 Cp6 2 l peak output current (note 2) p3 0 Cp3 7 , p5 2 , p5 3 h average output current (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 h average output current (note 3) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l average output current (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 l average output current (note 3) p4 0 Cp4 7 , p5 0 , p5 1 , p5 4 Cp5 7 , p6 0 Cp6 2 l average output current (note 3) p3 0 Cp3 7 , p5 2 , p5 3 i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) limits ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma parameter min. typ. max. symbol unit C20 C20 20 20 110 C10 C10 10 10 90 C1.0 C5.0 10 10 30 C0.5 C2.5 5.0 5.0 15 table 13 recommended operating conditions (vcc = 1.8 to 5.5 v, ta = C20 to 85c, unless otherwise noted) notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is average value measured over 100 ms.
55 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 14 recommended operating conditions (mask rom version) (vcc = 1.8 to 5.5 v, ta = C20 to 85c, unless otherwise noted) timer x and timer y input frequency (duty cycle 50%) system clock frequency main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(cntr 0 ) f(cntr 1 ) f( ) f(x in ) f(x cin ) limits mhz mhz mhz mhz mhz mhz khz parameter min. typ. 32.768 max. 4.0 (15 ? v cc C16)/11 8.0 (30 ? v cc C32)/11 8.0 20 ? v cc C32 50 symbol unit (4.0 v v cc 5.5 v) (v cc 4.0 v) (4.0 v v cc 5.5 v) (v cc 4.0 v) (2.0 v v cc 5.5 v) (v cc 2.0 v) notes 1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. i oh = C1 ma i oh = C0.25 ma v cc = 1.8 v i oh = C5 ma i oh = C1.5 ma i oh = C1.25 ma v cc = 1.8 v i ol = 10 ma i ol = 3 ma i ol = 2.5 ma v cc = 1.8 v i ol = 15 ma i ol = 4 ma v cc = 1.8 v v i = v cc v i = v cc v i = v cc v i = v ss pull-up off v cc = 5.0 v, v i = v ss pull-up on v cc = 1.8 v, v i = v ss pull-up on v i = v ss v i = v ss h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 h output voltage p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7, p4 0 Cp4 7 , p5 0 , p5 1 , p5 4 Cp5 7, p6 0 Cp6 2 l output voltage p3 0 Cp3 7 , p5 2 , p5 3 hysteresis int 0 Cint 2 , cntr 0 , cntr 1 , p0 0 Cp0 3 , p5 4 Cp5 7 hysteresis s clk1 , s clk2 , rxd 1 , rxd 2 hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 l input current reset l input current x in limits v v v v v v v v v v v v v a a a a a a a a parameter min. v cc C2.0 v cc C0.8 v cc C2.0 v cc C0.5 v cc C0.8 C60 C5.0 typ. 0.5 0.5 0.5 4.0 C120 C20 C4.0 max. 2.0 0.5 0.8 2.0 0.8 5.0 5.0 C5.0 C240 C40 C5.0 symbol unit test conditions v oh v oh v ol v ol v t+ Cv t- v t+ Cv t- v t+ Cv t- i ih i ih i ih i il i il i il electrical characteristics table 15 electrical characteristics (mask rom version) (vcc = 4.0 to 5.5 v, ta = C20 to 85c, unless otherwise noted)
56 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. ram hold voltage power source current limits parameter min. 1.8 typ. 5.1 1.0 14 6 7 3 0.1 max. 5.5 7.5 2.0 21 10 12 6 1.0 10 symbol unit when clock is stopped through mode, vcc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off, a-d converter in operating through mode, vcc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off, a-d converter stopped low-speed mode, v cc = 5 v, ta 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 5 v, ta = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode, v cc = 3 v, ta 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode, v cc = 3 v, ta = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off test conditions v ram i cc v ma ma a a a a a a ta = 25 c ta = 85 c table 16 electrical characteristics (mask rom version) (vcc = 1.8 to 5.5 v, ta = C20 to 85c, unless otherwise noted)
57 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter characteristics table 17 a-d converter characteristics (mask rom version) (vcc = 2.2 to 5.5 v, vss = av ss = 0 v, ta = C20 to 85c, port state = stopped, unless otherwise noted) resolution differencial non-linearity error non-linearity error off-set error full-scale error differencial non-linearity error non-linearity error off-set error full-scale error conversion time ladder resistor reference input current analog input current unit bits lsb lsb s k ? a a limits parameter min. 12 50 typ. 35 150 max. 10 1 1 3 5 1 1 2 3 tc(x in ) ? 121 (note) 100 200 5.0 symbol v cc = v ref = 5 v ? v cc = v ref = 2.2 v, ad clock frequency = 250 khz ? v cc = v ref = 2.3 v, ad clock frequency = 500 khz ? v cc = v ref = 2.4 v, ad clock frequency = 1 mhz ? v cc = v ref = 2.5 v, ad clock frequency = 2 mhz ? v cc = v ref = 2.5 v, ad clock frequency = 4 mhz ? v cc = v ref = 2.6 v, ad clock frequency = 8 mhz ad conversion clock selection bit :frequency not divided, 10bitad mode v ref = 5 v test conditions t conv r ladder iv ref i ia note: when frequency/2, 4 or 8 is selected by the ad conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8. lcd power supply characteristics table 18 lcd power supply characteristics (when connecting division resistors for lcd power supply) (vcc = 1.8 to 5.5 v, ta = C20 to 85c, unless otherwise noted) division resistor for lcd power supply (note) unit k ? limits parameter min. typ. 200 5 120 90 150 120 170 150 190 170 150 120 170 150 190 170 190 190 max. symbol rsel = 10 rsel = 11 lcd drive timing a lcd circuit division ratio = divided by 1 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 2 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 4 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 8 rsel = 01 rsel = 00 lcd drive timing b lcd circuit division ratio = divided by 1 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 2 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 4 rsel = 01 rsel = 00 lcd circuit division ratio = divided by 8 rsel = 01 rsel = 00 test conditions r lcd note: the value is the average of each one division resistor.
58 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd-s clk ) t h (s clk -rxd) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 C int 2 input h pulse width int 0 C int 2 input l pulse width serial i/o1, 2 clock input cycle time (note) serial i/o1, 2 clock input h pulse width (note) serial i/o1, 2 clock input l pulse width (note) serial i/o1, 2 input setup time serial i/o1, 2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd-s clk ) t h (s clk -rxd) limits s ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 typ. max. symbol unit limits s ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 45 40 11000/(15 ? v cc C 16) tc(cntr)/2 C 20 tc(cntr)/2 C 20 230 230 2000 950 950 400 200 typ. max. symbol unit reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 C int 2 input h pulse width int 0 C int 2 input l pulse width serial i/o1, 2 clock input cycle time (note) serial i/o1, 2 clock input h pulse width (note) serial i/o1, 2 clock input l pulse width (note) serial i/o1, 2 input setup time serial i/o1, 2 input hold time table 20 timing requirements 2 (vcc = 1.8 to 4.0 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) timing requirements and switching characteristics table 19 timing requirements 1 (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) note : when bit 6 of address 0fe0 16 or 0fe3 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 0fe0 16 or 0fe3 16 is 0 (uart). note : when bit 6 of address 0fe0 16 or 0fe3 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 0fe0 16 or 0fe3 16 is 0 (uart).
59 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. t wh (s clk ) t wl (s clk ) t d (s clk -txd) t v (s clk -txd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) t wh (s clk ) t wl (s clk ) t d (s clk -txd) t v (s clk -txd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) limits parameter min. t c (s clk )/2 C 30 t c (s clk )/2 C 30 C 30 typ. 10 10 max. 140 30 30 30 30 symbol unit ns ns ns ns ns ns ns ns notes 1: when the p-channel output disable bit (bit 4 of address 0fe1 16 or 0fe4 16 ) is 0. 2: the x out , x cout pins are excluded. serial i/o1, 2 clock output h pulse width serial i/o1, 2 clock output l pulse width serial i/o1, 2 output delay time (note 1) serial i/o1, 2 output valid time (note 1) serial i/o1, 2 clock output rising time serial i/o1, 2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) table 21 switching characteristics 1 (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) limits ns ns ns ns ns ns ns ns parameter min. t c (s clk )/2 C 50 t c (s clk )/2 C 50 C 30 typ. 20 20 max. 350 50 50 50 50 symbol unit serial i/o1, 2 clock output h pulse width serial i/o1, 2 clock output l pulse width serial i/o1, 2 output delay time (note 1) serial i/o1, 2 output valid time (note 1) serial i/o1, 2 clock output rising time serial i/o1, 2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) table 22 switching characteristics 2 (vcc = 1.8 to 4.0 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) notes 1: when the p-channel output disable bit (bit 4 of address 0fe1 16 or 0fe4 16 ) is 0. 2: the x out , x cout pins are excluded. fig. 56 circuit for measuring output switching characteristics measurement output pin 100pf c m o s o u t p u t measurement output pin 100pf n-channel open-drain output (note) 1 k ? note: when bit 4 of the uart control register (address 0ef1 16 or 0fe4 16 ) is 1. (n-channel open-drain output mode)
60 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 57 timing chart cntr 0 ,cntr 1 i n t 0 t o i n t 2 0.2v cc t d ( s c l k - t x d ) t f 0.2v cc 0 . 8 v c c 0 . 8 v c c t r t s u ( r x d - s c l k )t h ( s c l k - r x d ) t v (s clk -t x d) t c (s clk ) t w l ( s c l k ) t w h ( s c l k ) t x d 1 t x d 2 r x d 1 r x d 2 s clk1 s clk2 0 . 2 v c c t wl (x in ) 0.8v cc t wh (x in ) t c ( x i n ) x in 0.2v cc 0 . 8 v c c t w ( r e s e t ) r e s e t 0 . 2 v c c t wl (cntr) 0.8v cc t wh (cntr) t c ( c n t r ) 0 . 2 v c c t wl (int) 0.8v cc t wh (int)
61 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. package outline qfp64-p-1414-0.80 1.11 weight(g) C jedec code eiaj package code lead material alloy 42 64p6n-a plastic 64pin 14 ? 14mm body qfp C C CC C C CC C C C C C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.5 C C i 2 1.3 C C m d 14.6 C C m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.8 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 64 49 32 48 33 17 16 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f x CC 0.2 b x m lqfp64-p-1010-0.50 C weight(g) C jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 ? 10mm body lqfp C 0.1 C CC 0.2 C C CC C C C C C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 C C i 2 1.0 C C m d 10.4 C C m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 64 49 48 33 32 17 16 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 C C 0.6 0.25 C 0.75 C 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e
? 2000 mitsubishi electric corp. 0008 printed in japan (rod) ii new publication, effective aug. 2000. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan 38C2 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change.
rev. rev. no. date 1.0 first edition 000830 1.1 p53 table 12 recommended operating condition 000901 parameter of v ih , v il : x in (wrong) x in , x cin (correct) revision description list 38C2 group data sheet (1/1) revision description

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